The NVIDIA Jetson AGX Xavier GPIO Header Pinout table has been updated with the Linux GPIO numbering and work sheets mapping the Tegra pins all the way to the GPIO Expansion Header.
Note: The table is kept on a separate web page for easier maintenance. There’s a lot of info there, and sometimes needs updating. You can access the pinout table directly from the ‘Pinouts’ pull down menu on the top menu bar of the JetsonHacks website.
Background
GPIO means General Purpose Input/Output. These digital signal pins are uncommited pins which are controllable by the user at run time, acting as an input or output.
A table called the “device tree” determines the mapping between pins on the Tegra Xavier chip, module board and developer carrier board. The default device tree maps the GPIO Expansion Header pins to GPIO values, with the exception of the power/ground pins, I2C pins, and UART. Both the I2C pins and UART have associated hardware, which means that in practice they cannot be used for GPIO.
J30, the GPIO Expansion Header on the Xavier provides external access to GPIO and SFIO signals. In general, the pin layout is similar to the 40-pin Raspberry Pi.
Recommended Usage
NVIDIA has recommendations for how a developer should layout the GPIO Expansion Header pins if they are to implement Specific Function Input/Output (SFIO). Examples of SFIO are SPI, PWM, CANBUS and I2S.
Note that while these are very strong recommendations, you are free to use the pins to meet your needs. The basic idea here is that NVIDIA may use these pins for those specific functions some time in the future. Also, it’s a good idea that everyone uses the same layout when possible. For example, it makes sense if you are adding a CANBUS interface to use the designated pins.
I2C
As noted, the Xavier I2C has dedicated hardware for I2C. The I2C pins connect to a specific I2C controller bus:
Pins 3 and 5 are on I2C bus 8. For detection:
$ sudo i2cdetect -y -r 8
Pins 27 and 28 are on I2C bus 1. For detection:
$ sudo i2cdetect -y -r 1
Conclusion
When you start exploring the GPIO Expansion Header, this little map should provide quite useful.
Notes: Additional Reference Material
Additional information for values in the table and notes are take from Section 3.3 Expansion Header and Table 18. Expansion Header Pin Descriptions in the document “NVIDIA Jetson Xavier Developer Kit Carrier Board Specification” available from the NVIDIA Developer download center.
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